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CHIP

Semiconductor System Lab

Through this homepage, we would like to share our sweats, pains,
excitements and experiences with you.

CHIP 2002

CHIP 목록
Image Title Specifications

2002

Motion Express

Technology

Chip Size

Function


Clock Frequency

Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm Hynix CMOS DRAM Technology

6 mm x 6 mm

A MPEG
- 4 acceleration IP for Portable Video Application

27 MHz

~10,000

2.5 V(core), 3.3 V(I/O)

< 6 mW

Oct. 2002

2002

Motion Express

Technology

Chip Size

Function


Clock Frequency

Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm Hynix CMOS DRAM Technology

6 mm x 6 mm

A MPEG
- 4 acceleration IP for Portable Video Application

27 MHz

~10,000

2.5 V(core), 3.3 V(I/O)

< 6 mW

Oct. 2002

2002

RamP- IV

Technology

Chip Size

Function


Clock Frequency


Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm Hynix CMOS DRAM Technology

6 mm x 6 mm
- 3D Graphic Processor for Mobile Application
- 132/33 MHz for FAST mode

66/16.5 MHz for NORMAL mode
33/8.25 MHz for SLOW mode

60,000,000

2.3 V

210 mW

Oct. 2002

2002

RamP- IV

Technology

Chip Size

Function


Clock Frequency


Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm Hynix CMOS DRAM Technology

6 mm x 6 mm
- 3D Graphic Processor for Mobile Application
- 132/33 MHz for FAST mode

66/16.5 MHz for NORMAL mode
33/8.25 MHz for SLOW mode

60,000,000

2.3 V

210 mW

Oct. 2002

2002

An 800MHz Star-Connected On-Chip Network

Technology

Chip Size

Function


Clock Frequency


Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm DRAM Technology with 3 AI

10.8 mm x 6.0 mm
- On-chip packet transaction with plesiochronous communication
- Off-chip packet transaction for scalability

core @ 800 MHz
IP Block @ 200 MHz

81,000 (without 1 Kb SRAM)

2.3 V

264 mW

Oct. 2002

2002

An 800MHz Star-Connected On-Chip Network

Technology

Chip Size

Function


Clock Frequency


Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm DRAM Technology with 3 AI

10.8 mm x 6.0 mm
- On-chip packet transaction with plesiochronous communication
- Off-chip packet transaction for scalability

core @ 800 MHz
IP Block @ 200 MHz

81,000 (without 1 Kb SRAM)

2.3 V

264 mW

Oct. 2002

2002

10 Gbps/port 8x8 Shared-bus Switch Fabric

Technology

Chip Size

Function


Clock Frequency


Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm DRAM Technology with 3 AI

4 mm x 9 mm

10 Gbps/port 8x8 Shared-bus witch fabric with Hierarchical Output
Buffer

200 MHz for Dual port SRAM
20 MHz for Embedded DRAM (w/ 512 bits I/O)

32 Kb SRAM, 1 Mb DRAM

2.3 V

240 mW

Oct. 2002

2002

10 Gbps/port 8x8 Shared-bus Switch Fabric

Technology

Chip Size

Function


Clock Frequency


Transistor Counts

Power Supply

Power Consumption

Released Date

0.16 μm DRAM Technology with 3 AI

4 mm x 9 mm

10 Gbps/port 8x8 Shared-bus witch fabric with Hierarchical Output
Buffer

200 MHz for Dual port SRAM
20 MHz for Embedded DRAM (w/ 512 bits I/O)

32 Kb SRAM, 1 Mb DRAM

2.3 V

240 mW

Oct. 2002

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