In this article, we propose the C-Transformer with the big-little network, and implicit weight generation (IWG) to solve the external memory bottleneck of large language models. It has 3 feature functional blocks: 1) Homogeneous DNN-Transformer/Spiking-transformer core with hybrid multiplication/accumulation unit to increase HW utilization; 2) Output spike speculation unit to increase the energy efficiency of spike domain p…

In this paper, we propose a Complementary-Deep-Neural-Network (C-DNN) processor by combining CNN and SNN to take advantage of them. The C-DNN processor can support both complementary inference and training with heterogenous CNN and SNN core architecture. In addition, the C-DNN processor is the first DNN accelerator AISC that can support CNN-SNN workload division by using their magnitude-energy trade-off. The proposed proces…

In this paper, we propose SNPU, a spike-domain DNN accelerator, to achieve ultralow power consumption with neuron-level event-driven inference. The spike domain processing can replace many MACs with small number of accumulations. The proposed SNPU has 3 key features; spike train decomposition to reduce the accumulations, time shrinking multi-level encoding to replace the multiple accumulations with single shift-and-accumula…

Previous CIM AI processors did not achieve high energy efficiency >100 TOPS/W because they need multiple WL driving for parallelism and many high-precision ADCs for high accuracy. Some CIMs heavily exploited weight data sparsity to obtain high energy efficiency, but their sparsity was limited to <30% in practical cases (e.g. ImageNet task with ResNet-18) to secure <1% accuracy loss. In this paper, we propose the Ne…